Moving forward, as we enter the advanced packaging era, we see gains in transistor density being delivered by our packaging. Packaging served as the vehicle through which the benefits of Moore’s Law were realized. These connections supported more functionality in the silicon, which was needed for Moore’s Law scaling. Each evolution in that era – from wire bond and lead frame packages, to flip chip technology on ceramic substrates, to the adoption of organic substrates and introduction of multi-chip packages – brought an increased number of connections. Until the 2010s, the primary role of packaging was to route power and signaling between the motherboard and silicon, and to protect the silicon. The role of packaging and its contribution to Moore’s Law scaling is evolving. As we said in July 2021, as we implement these innovations and others, we expect to achieve transistor performance per watt parity by 2024 and leadership by 2025. These gains are achieved through several innovations, including backend metal resistance and capacitance improvements, transistor architecture and library architecture improvements.
After the introduction of RibbonFET and PowerVia with Intel 20A and Intel 18A, new follow-on process nodes are already in development delivering additional gains in power, performance and density. Intel is in close partnership with ASML and other ecosystem partners to be the first to bring this technology into high-volume production. The next generation of extreme ultraviolet (EUV) lithography, High Numerical Aperture or “High NA,” brings further improvements in resolution and error reduction, delivering a reduction in process complexity with an increased flexibility in design rules. By separating power and signal, you can use the metal layers more effectively, as there are fewer trade-offs to make. Previously, power came from the top of the die and “competed” with signal interconnects. At the same time, we also deliver PowerVia, the industry’s first backside power delivery architecture. RibbonFET delivers faster transistor switching speeds with the same drive current in a smaller footprint. RibbonFET represents our first new transistor architecture since FinFET. Intel’s next great architectural innovation is RibbonFET, our implementation of the gate-all-around (GAA) transistor, arriving with Intel 20A. By the late 2000s, as physical dimensions continued to shrink, the industry realized that additional areas of innovation, including materials science, new process architecture and design technology co-optimization (DTCO), were needed to keep pace. With inventions such as high-k metal gate technology, tri-gate 3D transistors and strained silicon, Intel has consistently delivered groundbreaking technologies to maintain pace with Moore's Law. Intel has a long, rich history of foundational process innovations in pursuit of Moore’s Law, as seen in Figure 2. Intel engineers and scientists have continually faced - then overcome - the challenges posed by physics when the features on a chip shrink to the size of atoms. This demand for more and more computing power is the push for the industry to maintain the pace of Moore’s Law. We are projecting that by the end of this decade, on average, all of us will have 1 petaflop (10 15 floating-point operations per second) of compute and 1 petabyte of data less than 1 millisecond away 3. For example, the world creates nearly 270,000 petabytes (i.e. Everything is becoming digital, with four key superpowers.” The superpowers – ubiquitous computing, cloud-to-edge infrastructure, pervasive connectivity and artificial intelligence – are set to transcend and transform the world. At this time we see no end to the demand for compute, and more compute continues to push the industry for more innovation. Intel CEO Pat Gelsinger has shared: “Technology has never been more important for humanity than it is now. The rate of digitalization of the world surged over the past two years, triggered by the COVID-19 pandemic, and this enhanced transition was enabled by the semiconductor industry and its innovation. The more transistors or components on a device, the cost per device is reduced while the performance per device is increased. This prediction became known as Moore’s Law and is depicted in Figure 1. In 1965, Intel co-founder Gordon Moore predicted that the number of transistors on a chip would double roughly every two years, with a minimal rise in cost 1.
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